Memory devices provide data storage for electronic systems. One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that may be erased and reprogrammed in blocks. Many modern personal computers have BIOS stored on a flash memory chip. Such BIOS is sometimes called flash BIOS.
Flash memory is also popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. The cells are usually grouped into blocks. Each of the cells within a block may be electrically programmed by charging a floating gate. The charge may be removed from the floating gate by a block erase operation. Data is stored in a cell as charge in the floating gate.
NAND is a basic architecture of flash memory. A NAND cell unit comprises at least one select gate coupled in series to a serial combination of memory cells (with the serial combination being commonly referred to as a NAND string).
Flash memory, or more generally EEPROM, incorporate charge storage structures into transistor gates, and incorporate control gate structures over the charge storage structures. The charge storage structures may be immediately over gate dielectric. The charge storage structures may, for instance, comprise floating gate material or charge-trapping material. The amount of charge stored in the charge storage structures determines a programming state. In contrast, standard field effect transistors (FETs) do not utilize charge storage structures as part of the transistors, but instead have a conductive gate directly over gate dielectric material. EEPROM, such as flash, may be referred to as charge storage transistors to indicate that charge storage structures are incorporated into the transistors. The gates of the charge storage transistors may be referred to as charge storage transistor gates.
It is desired to form the select gates to be standard field effect transistors (FETs), rather than charge storage transistors, and to form the string gates as charge storage transistors. Yet, it is also desired to utilize common processing steps for fabrication of the select gates and string gates. This is creating difficulties with conventional processing, and accordingly it is desired to develop new processing for fabrication of the select gates and string gates. Also, numerous peripheral gates may be formed adjacent a NAND memory array and utilized for controlling reading and writing relative to the memory array. It would be desired to develop processing which utilized common process steps for fabrication of the peripheral gates, string gates and select gates.
Although charge storage transistors (i.e., EEPROM transistors) of NAND have traditionally utilized floating gate material (for instance, polycrystalline silicon) for retaining charge, there has been substantial interest in replacing the floating gate material with charge trapping material (for instance, silicon nitride and/or conductive nanodots). It would be desirable for the processing utilized for fabrication of string gates, select gates, and peripheral gates to be generally applicable for applications in which the string gates correspond to charge storage transistor gates utilizing floating gate material, as well as to applications in which the string gates correspond to charge storage transistor gates utilizing charge-trapping material.